The present invention relates to an AD converter and an AD conversion method. For example, the present invention relates to a successive approximation AD converter and a successive approximation AD conversion method.
A successive approximation ADC is known as an AD (Analog/Digital) converter (ADC) that converts an input analog signal into a digital signal. The successive approximation ADC samples an input analog signal, performs a successive approximation process on a sampling value, and outputs a digital signal representing the successive approximation result.
Semiconductor devices having the ADC mounted thereon are widely used for, for example, control devices and sensors for vehicles. In such semiconductor devices, there is a demand for reducing the number of external terminals to satisfy the demand for miniaturization. In order to reduce the number of external terminals, a technique for sharing a power supply terminal for supplying a power supply voltage, a reference voltage, and the like has been developed. Such semiconductor devices, however, have a problem that the AD conversion accuracy deteriorates due to reference noise.
Measures for reducing the effect of noise in the successive approximation ADC have been conventionally studied (for example, Japanese Unexamined Patent Application Publication No. 2014-11768). A successive approximation ADC disclosed in Japanese Unexamined Patent Application Publication No. 2014-11768 includes a DA (Digital/Analog) converter (DAC), a comparator, a successive approximation register (SAR) logic unit, and a reference voltage generation circuit.
The DAC has a function for sampling an input analog signal, and includes a plurality of capacitor elements charged during the sampling process. The comparator performs successive approximation of the output of the DAC and the output of the reference voltage generation circuit, and calculates a digital signal to be output. The successive approximation logic unit includes a successive approximation register, and the value of the successive approximation register is overwritten according to the comparison result of the comparator.
During the successive approximation process, the plurality of capacitor elements are connected to a high-side reference voltage or a low-side reference voltage according to the value of the successive approximation register, and a comparison voltage used for the subsequent successive approximation process is generated. When the digital value (code value) output from the successive approximation AD converter is large, the number of capacitor elements connected to the high-side reference voltage increases. When the code value is small, the number of capacitor elements connected to the low-side reference voltage increases.
A reference voltage generation circuit having a general configuration includes one capacitor element connected only to the low-side reference voltage. Accordingly, the reference voltage generation circuit having a general configuration has noise sensitivity characteristics related only to the low-side reference voltage. For this reason, the difference between the amount of noise generated in the output of the DAC and the amount of noise generated in the output of the reference voltage generation circuit increases as the code value increases.
On the other hand, in Japanese Unexamined Patent Application Publication No. 2014-11768, the reference voltage generation circuit includes a first capacitor element connected to the high-side reference voltage, and a second capacitor element connected to the low-side reference voltage. Accordingly, the reference voltage generation circuit disclosed in Japanese Unexamined Patent Application Publication No. 2014-11768 has noise sensitivity characteristics related to both the high-side reference voltage and the low-side reference voltage. Thus, even when the code value increases, the difference between the amount of noise generated in the output of the DAC and the amount of noise generated in the output of the reference voltage generation circuit can be reduced.